1. Field of the Invention
The present invention relates generally to the field of computer memory, and more particularly, to a dynamic random access memory dual in-line memory module.
2. Related Art
Dynamic, random access memory (DRAM) single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs) are preferred implementations of semiconductor main memory in computer systems of all sizes, including personal computers (PCs), workstations, supercomputers and the like. Both SIMMs and DIMMs include a printed circuit board (PCB) having an edge connector with a plurality of signal pads on opposite sides of the PCB for physical and electrical connection to a connector socket. DRAM or synchronous DRAM integrated circuit chips are mounted on the PCB, and are electrically connected to various connector signal pads. A SIMM has opposing signal pads electrically connected so that each pair carries a single signal. In a DIMM, opposing pads are not connected so that each pad can carry a separate signal. However, the terms SIMM and DIMM are often used synonymously in the memory art. A detailed description of a known DRAM SIMM can be found in commonly owned U.S. Patent No. 5,272,664 to Alexander et al., the full text of which is incorporated herein by reference.
In a multiprocessor computer system, main memory may be implemented as distributed shared memory or centralized (i.e., non-distributed) memory. Each processor generally has a local cache. Thus, the processors must maintain cache coherence. Most existing multiprocessors with cache coherence rely on snooping to maintain coherence. To accomplish this, all processors are connected to a common bus. The processors "snoop" the bus. That is, the information about which processors are caching which data items is distributed among all of the caches. Thus, straightforward snooping schemes require that all caches see every memory request from every processor. This inherently limits the scalability of these systems because the common bus and the individual processor caches eventually saturate. With today's high-performance RISC processors, this saturation can occur with just a few processors.
Directory structures avoid the scalability problems of snoopy schemes by removing the need to broadcast every memory request to all processor caches. The directory maintains pointers to the processor caches holding a copy of each memory block. Only the caches with copies can be affected by an access to the memory block, and only those caches need be notified of the access. Thus, the processor caches and interconnect will not saturate due to coherence requests. Furthermore, directory-based coherence is not dependent on any specific interconnection network like the bus used by most snooping schemes.
Few DSM multiprocessors that use directory structures have been developed. Examples of such DSM systems include Stanford University's Dash multiprocessor described in Lenoski, Daniel, et al., "The Stanford Dash Multiprocessor," IEEE, pp. 63-79, March 1992; Massachusetts Institute of Technology's (MIT) Alewife multiprocessor described in Chaiken, David, et al., "LimitLESS Directories: A Scalable Cache Coherence Scheme," ACM, pp. 224-234, 1991; and Convex Computer Corporation's Exemplar multiprocessor described in Brewer, Tony, "A Highly Scalable System Utilizing up to 128 PA-RISC Processors," IEEE, pp. 133-140, 1995.
In the Stanford Dash multiprocessor, the main memory was hardwired for maximum memory capacity.1 In the MIT multiprocessor and the Convex Computer Corporation multiprocessor, directory information was stored in main memory. Thus, the data and the directory information had to be accessed sequentially, limiting memory bandwidth.
What is needed is a technique for implementing main memory in a DSM multiprocessor computer system in a manner such that directory information is accommodated and such that straightforward memory expansion of both data memory and directory memory are concurrently supported.